The present invention relates to technology useful for buried epitaxial growth technology used in a method for manufacturing a semiconductor device (or semiconductor integrated circuit device) and peripheral technology.
Japanese Unexamined Patent Publication No. 2007-201499 discloses a technique which forms a trench for an alignment target before the formation of a trench for a superjunction or forms both trenches virtually at the same time in a process of manufacturing a power semiconductor device.
Japanese Unexamined Patent Publication No. 2008-171972 discloses a technique which forms a trench for an alignment target before the formation of a trench for a superjunction in a process of manufacturing a power semiconductor device.
Japanese Unexamined Patent Publication No. 2009-224606 discloses a technique which forms a trench for an alignment target virtually at the same time as a trench for a superjunction in a process of manufacturing a power semiconductor device.